Sunday, 07 March 2021

AccelerComm Unveils Fully Integrated PUSCH Decoder to Supercharge 5G NR for Performance-Critical Channels

posted by AccelerComm
Thursday 18 February 21

AccelerComm, the channel coding specialist, is supercharging 5G NR with cutting edge Physical Layer IP which increases spectral efficiency and reduces latency. The company today announced a complete high-performance 5G NR PUSCH (Physical Uplink Shared Channel) Decoder and PDSCH (Physical Downlink Shared Channel) Encoder for customers who want to maximize the efficacy of their 5G radio network…

AccelerComm, the channel coding specialist, is supercharging 5G NR with cutting edge Physical Layer IP which increases spectral efficiency and reduces latency. The company today announced a complete high-performance 5G NR PUSCH (Physical Uplink Shared Channel) Decoder and PDSCH (Physical Downlink Shared Channel) Encoder for customers who want to maximize the efficacy of their 5G radio network. AccelerComm will be presenting the PUSCH Decoder and other channel coding solutions to attendees of MWC Shanghai – to book a virtual meeting, click here: https://www.accelercomm.com/mobile-world-congress-shanghai

Building on the company’s carrier-grade portfolio of channel coding and modulation/demodulation IP, this highly integrated solution enables 5G base stations to benefit from AccelerComm’s proven best-in-class LDPC decoder performance, whilst minimising time to market.

“Spectrum is a scarce resource, and is the key asset owned by mobile operators, so it is critical that they maximize its use - every dB counts,” said Robert Barnes, VP Sales & Marketing of AccelerComm. “This product builds on the existing AccelerComm IP portfolio to enable operators to deliver on the high-performance, low-latency promise of 5G using their existing spectrum and cloud RAN infrastructure.”

AccelerComm’s PUSCH Decoder integrates additional 3GPP physical layer functions together with its high-performance LDPC decoders, to create a 3GPP-compliant IP package that can be quickly integrated and optimized for use in custom silicon (ASIC) and programmable hardware (FPGA). The flexible architecture means that it can be customized depending on an operator’s service requirements, resulting in optimal performance, power, and silicon area, tailored to their specific needs.

This latest product from AccelerComm adds new blocks of IP to complete the link between the LDPC decoder and the MIMO detector:

• gNodeB uplink stack (PUSCH Decoder)
o LDPC decoder with transport block wrapper, polar decoder, demultiplexer, descrambler and QAM demodulator
• gNodeB downlink stack (PDSCH Encoder)
o LDPC encoder with transport block wrapper, scrambler, and QAM modulator

The specification is as defined in Sections 6.2 and 7.2 of 3GPP document TS 38.212, as well as Sections 6.3.1.1, 6.3.1.2, 7.3.1.1 and 7.3.1.2?of TS 38.211. 
 


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